• Product: Low-power, mixed-signal ASIC with embedded ARM Cortex M3 and Flash NVM
• Role: Technical project lead
• Design activities:
• Designed DMA and system / peripheral bus structure
• Integrated USB IP
• Architected power-up sequencing and managed analog-digital interface
• Designed HW hooks for FW optimization
• Collaborated effectively with remote FW team and test / qualification group

• Product: Characterization & qualification test vehicle for 90nm rad-hard process
• Role: Project lead
• Design activities:
• Defined and designed entire chip - 1 million transistors
• Implemented DFT structures to achieve required 99% fault coverage
• Developed test plan and extensive characterization/qualification test patterns
• Assisted test house in test pattern debug on tester
• Collaborated effectively with remote customer, remote IP developer and remote test house

• Product: Die-area-critical, mixed-signal ASIC
• Role: Project lead
• Design activities:
  • Defined and designed digital core
  • Specified analog-digital interface and test hooks
  • Implemented cascaded state machines in dense fashion to achieve extra space for analog
• Collaborated effectively with remote customer, remote analog designer and remote digital physical design team
• Met aggressive schedule

• Role: Digital Backend Lead
• Activities:
• Defined and documented backend flow and tools to be used
• Wrote command and run scripts for SYN, STA and LEC for multiple tools
• Implemented Cadence EDI foundation flow for P&R and enhanced scripts
• Flow features:
• Customizable core flow with separate constraints input
• Flow was successfully reused from project to project
• Achieved database integrity and repeatable quality with multi-person backend team
• Trained others in use of flow